ZL30110 Datasheet - Zarlink Semiconductor

ZL30110 Telecom Rate Conversion DPLL

The ZL30110 clock rate conversion digital phaselocked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is con.

ZL30110 Features

* Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz

* Provides a range of output clocks:

* 65.536 MHz TDM clock locked to the input reference

* General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator

* General purpose 1

ZL30110 Datasheet (320.76 KB)