ZL30110 - Telecom Rate Conversion DPLL

Zarlink Semiconductor

Datasheet Details

The ZL30110 clock rate conversion digital phaselocked loop (DPLL) provides accurate and reliable frequency conversion.

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz.
Provides a range of output clocks:.
65.536 MHz TDM clock locked to the input reference.
General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator.
General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator.
Provides DPLL lock and reference fail indication.
Automatic free run mode on reference fail.
DPLL.

📁 Related Datasheet

ZL30100 - T1/E1 System Synchronizer (Zarlink Semiconductor Inc)
ZL30101 - T1/E1 Stratum 3 System Synchronizer (Zarlink Semiconductor Inc)
ZL30106 - SONET/SDH/PDH Network Interface DPLL (Zarlink)
ZL30130 - Stratum 2/3/3E System Synchronizer/SETS (Microsemi)
ZL30136 - Network Interface Synchronizer (Microsemi)
ZL30138 - Stratum 2/3/3E System Synchronizer/SETS (Microsemi)
ZL30142 - SyncE SONET/SDH G.8262/Stratum 3 System Synchronizer (Microsemi)
ZL30143 - SyncE SONET/SDH G.8262/Stratum3 System Synchronizer/SETS (Microsemi)

📌 All Tags

Zarlink Semiconductor ZL30110-like datasheet

ZL30110 Stock/Price