ZL30117 Datasheet - Zarlink Semiconductor

ZL30117 SONET/SDH Low Jitter Line Card Synchronizer

www.DataSheet4U.com ZL30117 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet February 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30117GGG 64 Pin CABGA Trays ZL30117GGG2 64 Pin CABGA Trays Pb Free Tin/Silver/Copper -40oC to +85oC Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3.

ZL30117 Features

* Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies from 6.48 MHz up to 622.08 MHz with jitter l

ZL30117_ZarlinkSemiconductor.pdf