ZL30119 - Low Jitter Line Card Synchronizer

Zarlink Semiconductor

Datasheet Details

12 1.1 DPLL

Ordering Information June 2006.
Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813.
Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64.
Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8 kHz up to 77.76.

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