ZL30102 Datasheet - Zarlink Semiconductor

ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer

The ZL30102 DS1/E1 Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for DS1/E1 transmission equipment deploying redundant network clocks. The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three netw.

ZL30102 Features

* Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock

* Supports Telcordia GR-1244-CORE Stratum 4 and 4E

* Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces

* Sup

ZL30102_ZarlinkSemiconductor.pdf