ZL30105 Datasheet (Zarlink Semiconductor) - T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer

ZL30105, T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer

The ZL30105 SDH/PDH System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SDH and T1/E1 transmission equipment.

It provides advanced support for systems deploying redundant clocks.

The ZL30105 generates SBI, ST-BUS and other TDM clock and fram

ZL30105 Features

* Synchronizes to clock-and-sync-pair to maintain minimal phase skew between the master-clock and the redundant slave-clock

* Supports ITU-T G.813 option 1, G.823 for 2048 kbit/s and G.824 for 1544 kbit/s interfaces

* Supports Telcordia GR-1244-CORE Stratum 3/4/4E

* S