ZL30107 Datasheet - Zarlink Semiconductor

ZL30107 GbE Line Card Synchronizer

Pin # B1 A3 B4 D8 G5 Name REF0 REF1 REF2 CLK RST I/O Type Id Description Shortform Data Sheet Reference Inputs (LVCMOS, Schmitt Trigger). These reference inputs are used for synchronizing the PLL. These pins are internally pulled down to Vss. SONET/SDH/Ethernet Clock Output (LVCMOS). This output c.

www.DataSheet4U.com ZL30107 GbE Line Card Synchronizer Shortform Data Sheet March 2007 A full Data Sheet is available to qualified customers. To register, please send an email to TimingandSync@zarlink.com. Ordering Information ZL30107GGG 64 Pin CABGA Trays ZL30107GGG2 64 Pin CABGA Trays Pb Free Tin/Silver/Copper -40oC to +85oC Configurable to accept a 25 MHz input reference Automatic entry into Asynchronous Holdov.

ZL30107 Features

* Single chip low cost solution for synchronizing an Ethernet PHY to a standard telecom clock Generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock Supports three modes of operation: Asynchronous Freerun, Synchronous, and Asynchronous Holdover Defa

ZL30107_ZarlinkSemiconductor.pdf