ZL30101
Zarlink Semiconductor Inc
421.69kb
T1/e1 stratum 3 system synchronizer. The ZL30101 Stratum 3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for
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📁 Related Datasheet
ZL30100 - T1/E1 System Synchronizer
(Zarlink Semiconductor Inc)
ZL30100 T1/E1 System Synchronizer
Data Sheet
Features
April 2010
• Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
• Supports ITU-T G.823.
ZL30102 - T1/E1 Stratum 4/4E Redundant System Clock Synchronizer
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ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to main.
ZL30105 - T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer
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ZL30105
T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTCA™ and H.110
Data Sheet
Features
• Synchronizes to clock-and-sync-pair .
ZL30106 - SONET/SDH/PDH Network Interface DPLL
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ZL30106 SONET/SDH/PDH Network Interface DPLL
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs .
ZL30107 - GbE Line Card Synchronizer
(Zarlink Semiconductor)
..
ZL30107 GbE Line Card Synchronizer
Shortform Data Sheet
March 2007
A full Data Sheet is available to qualified customers. To reg.
ZL30108 - SONET/SDH Network Interface DPLL
(Zarlink Semiconductor)
Features
• Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
• Accepts two input r.
ZL30109 - DS1/E1 System Synchronizer
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ZL30109 DS1/E1 System Synchronizer with
19.44 MHz Output
Data Sheet
Features
April 2010
• Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
.
ZL30110 - Telecom Rate Conversion DPLL
(Zarlink Semiconductor)
ZL30110 Tele Rate Conversion DPLL
Features
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
• Provides a range of output clocks:
• 65.5.
ZL30111 - POTS Line Card PLL
(Zarlink Semiconductor)
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ZL30111 POTS Line Card PLL
Data Sheet Features
• • • • • • • • • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input P.
ZL30112 - SLIC/CODEC DPLL
(Zarlink Semiconductor)
ZL30112 SLIC/CODEC DPLL
Data Sheet
Features
November 2009
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input
• Provides 2.048 MHz an.