ZL30100 Datasheet - Zarlink Semiconductor Inc

ZL30100, T1/E1 System Synchronizer

ZL30100 T1/E1 System Synchronizer Data Sheet .
The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1.

Features

* April 2010
* Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
* Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
* Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces Ordering Information ZL30100QDG1 64 Pin TQFP

Applications

* Synchronization and timing control for multi-trunk DS1/E1 systems such as DSLAMs, gateways and PBXs
* Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) buses
* Line Card synchronization for PDH systems
* Selectable loop filter ban

ZL30100_ZarlinkSemiconductorInc.pdf