( DataSheet : www.DataSheet4U.com ) www.DataSheet.
Hitachi Semiconductor
HD74LS74A - Dual D-type Positive Edge-triggered Flip-Flops
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
National Semiconductor
DM54LS74A - Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs
54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74.
Fairchild Semiconductor
DM74ALS74A - Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear September 1986 Revised February 2000 DM74ALS74A Dual D Positive-Edge-Trigg.
NXP
74ALS74A - Dual D-type flip-flop
INTEGRATED CIRCUITS 74ALS74A Dual D-type flip-flop with set and reset Product specification IC05 Data Handbook 1996 Jul 01 Philips Semiconductors P.
Motorola
SN54LS748 - 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS
10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decodi.
Motorola Inc
SN54LS74A - DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce.
ON Semiconductor
74LS74 - LOW-POWER SCHOTTKY
SN74LS74A Dual D-Type Positive Edge-Triggered Flip-Flop The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high sp.
Fairchild Semiconductor
74LS74 - Dual Positive-Edge-Triggered D Flip-Flops
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS74A Dual Posit.
Hitachi Semiconductor
74LS74 - Dual D-type Positive Edge-triggered Flip-Flops
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
National Semiconductor
74LS74 - Dual Positive-Edge-Triggered D Flip-Flops
54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74.
Motorola
74LS74 - DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce.
Motorola
SN74LS748 - 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS
10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decodi.
ON Semiconductor
SN74LS74A - Dual D-Type Positive Edge-Triggered Flip-Flop
SN74LS74A Dual D−Type Positive Edge−Triggered Flip−Flop The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high sp.
Motorola
SN74LS74A - DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D.
National Semiconductor
DM74LS74A - Dual Positive-Edge-Triggered D Flip-Flops
54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74.
Fairchild Semiconductor
DM74LS74A - Dual Positive-Edge-Triggered D Flip-Flops
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS74A Dual Posit.
Agere Systems
LS74 - Dual D-Type Positive Edge Triggered Flip-Flop
( DataSheet : www.DataSheet4U.com ) www.DataSheet4U.com .
National Semiconductor
54LS74 - Dual Positive-Edge-Triggered D Flip-Flops
www.DataSheet4U.com 54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS.
