Datasheet Summary
May 2001
®
4M×4 CMOS DRAM (EDO) family Features
- Organization: 4,194,304 words × 4 bits
- High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
- TTL-patible, three-state I/O
- JEDEC standard package
- 300 mil, 24/26-pin SOJ
- 300 mil, 24/26-pin TSOP
- Low power consumption
- Active: 908 mW max
- Standby: 5.5 mW max, CMOS I/O
- Extended data out
- Refresh
- 2048 refresh cycles, 32 ms refresh interval for AS4C4M4E1
- RAS-only or CAS-before-RAS refresh
- 5V power supply
- Latch-up current ≥ 200 mA
- ESD protection ≥ 2000 volts
- Industrial and mercial temperature available
Pin arrangement
VCC I/O0 I/O1 WE RAS NC A10...