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AS4C4M4E1 - 4M x 4 CMOS DRAM

Description

Address inputs Row address strobe Column address strobe Write enable Input/output Output enable Power Ground A0 to A10 t e U 4 .c m o I/O0 to I/O3 GND Symbol tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC5 AS4C4M4E1-50 50 25 12 13 85 25 135 2.0 AS4C4M4E1-60 60 30 15 15 100 30 120 Unit Alliance Semi

Features

  • Organization: 4,194,304 words × 4 bits.
  • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time.
  • TTL-compatible, three-state I/O.
  • JEDEC standard package - 300 mil, 24/26-pin SOJ - 300 mil, 24/26-pin TSOP.
  • Low power consumption - Active: 908 mW max - Standby: 5.5 mW max, CMOS I/O.
  • Extended data out.
  • Refresh - 2048 refresh cycles, 32 ms refresh interval for AS4C4M4E1 - RAS-only or CAS-.

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Datasheet Details

Part number AS4C4M4E1
Manufacturer Alliance Semiconductor
File Size 358.09 KB
Description 4M x 4 CMOS DRAM
Datasheet download datasheet AS4C4M4E1 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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May 2001 ® AS4C4M4E1 4M×4 CMOS DRAM (EDO) family Features • Organization: 4,194,304 words × 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time • TTL-compatible, three-state I/O • JEDEC standard package - 300 mil, 24/26-pin SOJ - 300 mil, 24/26-pin TSOP • Low power consumption - Active: 908 mW max - Standby: 5.
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