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AS4LC2M8S1 - (AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM

Download the AS4LC2M8S1 datasheet PDF. This datasheet also covers the AS4LC2M8S0 variant, as both devices belong to the same (as4lcxmxxsx) 3.3v 2m x 8/1m x 16 cmos synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

Output disable/write mask AS4LC2M8S1 and AS4LC2M8S0 AS4LC1M16S0 and AS4LC1M16S1 DataSheet4U.com VSSQ DQ9 DQ8 VCCQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS RA0 10 DataShee Address inputs CA0 7 (×16) CA0 8 (×8) Bank address (BA) Input/output Row address strobe Column

Key Features

  • Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0.
  • All signals referenced to positive edge of clock, fully synchronous.
  • Dual internal banks controlled by A11 (bank select).
  • High speed - 143/125/100 MHz - 7/8/10 ns clock access time.
  • Auto refresh and self refresh.
  • PC100 functionality.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS4LC2M8S0_AllianceSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS4LC2M8S1
Manufacturer Alliance Semiconductor
File Size 1.01 MB
Description (AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM
Datasheet download datasheet AS4LC2M8S1 Datasheet

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Other Datasheets by Alliance Semiconductor

Part Number Description
AS4LC2M8S0 (AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM
AS4LC256K16E0 3.3V 256K X 16 CMOS DRAM (EDO)
AS4LC1M16E5 3V 1M x 16 CMOS DRAM
AS4LC1M16S0 (AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM
AS4LC1M16S1 (AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com May 2001 Preliminary ® 3.3V 2M × 8/1M × 16 CMOS synchronous DRAM Features • Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0 • All signals referenced to positive edge of clock, fully synchronous • Dual internal banks controlled by A11 (bank select) • High speed - 143/125/100 MHz - 7/8/10 ns clock access time • Auto refresh and self refresh • PC100 functionality • Automatic and direct precharge including concurrent autoprecharge • Burst read, write/Single write • Random column address assertion in every cycle, pipelined operation • LVTTL compatible I/O • 3.