ASM5I9350 - 3.3V 1:10 LVCMOS PLL Clock Generator

Alliance Semiconductor

The ASM5I9350 by Alliance Semiconductor is a 3.3V 1:10 LVCMOS PLL Clock Generator. Below is the official datasheet preview.

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ASM5I9350 3.3V 1:10 LVCMOS PLL Clock Generator by Alliance Semiconductor - Datasheet Preview — Official preview page of the **ASM5I9350** 3.3V 1:10 LVCMOS PLL Clock Generator datasheet (Alliance Semiconductor).

Datasheet Details

Part number	ASM5I9350
Manufacturer	Alliance Semiconductor
File Size	510.54 KB
Description	3.3V 1:10 LVCMOS PLL Clock Generator
Datasheet	ASM5I9350_AllianceSemiconductor.pdf
Additional preview pages of the ASM5I9350 datasheet.

ASM5I9350 Product details

Description

The ASM5I9350 is a low-voltage high-performance does not apply.200MHz PLL-based clock driver designed for high speed clock distribution applications.Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com Notice: The information in this document is subject to change without notice.July 2005 rev 0.2 Block Diagram ASM5I9350 SELA PLL_EN REF_SEL TCLK XIN XOUT www.DataSheet4U.com osc Phase Detecto

Features

Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31.25 MHz 2.5V or 3.3V operation ASM5I9350 The ASM5I9350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table 2. These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS compatible output ca.

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Published: May 9, 2008 |