ASM5I9773A Overview
Key Features
- Each bank divides the VCO output per SEL(A:C) settings (see Table - Function Table (Configuration Controls))
- Each LVCMOS-compatible output can drive 50Ω series- or parallel-terminated transmission lines
- For series-terminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of 1:24
- The PLL is ensured stable, given that the VCO is configured to run between 200 MHz to 500 MHz
- This allows a wide range of output frequencies, from 8 MHz to 200 MHz
- For normal operation, the external feedback input FB_IN is connected to the feedback output FB_OUT
- The internal VCO is running at multiples of the input reference clock set by the feedback divider (see Table - Frequency Table)
- When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers
- This mode is fully static and the minimum input clock frequency specification does not apply
