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Alliance Semiconductor Corporation

AS7C33128PFD18B Datasheet Preview

AS7C33128PFD18B Datasheet

3.3V 128K x 18 pipeline burst synchronous SRAM

No Preview Available !

February 2005
AS7C33128PFD18B
®
3.3V 128K × 18 pipeline burst synchronous SRAM
Features
• Organization: 131,072 words × 18 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
www.DataSheet4IUn.dciovmidual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[16:0]
GWE
BWb
BWE
BWa
CCEE01
CE2
ZZ
OE
17
Power
down
LBO
CLK
CS Burst logic
CLR
DQ
CS Aredgdisrteesrs
CLK
17
15 17
128K × 18
Memory
array
D DQb Q
BryetgeisWterriste
CLK
D DQa Q
BryetgeisWterriste
CLK
D Enable Q
register
CE
CLK
D Enable Q
redgeilsatyer
CLK
18 18
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ [a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
–200
5
200
3.0
375
130
30
–166
6
166
3.5
350
100
30
–133
7.5
133
4
325
90
30
Units
ns
MHz
ns
mA
mA
mA
1/31/05; v.1.2
Alliance Semiconductor
P. 1 of 19
Copyright © Alliance Semiconductor. All rights reserved.




Alliance Semiconductor Corporation

AS7C33128PFD18B Datasheet Preview

AS7C33128PFD18B Datasheet

3.3V 128K x 18 pipeline burst synchronous SRAM

No Preview Available !

®
2 Mb Synchronous SRAM products list1,2
Org Part Number
128KX18
AS7C33128PFS18B
64KX32
AS7C3364PFS32B
64KX36
AS7C3364PFS36B
128KX18
AS7C33128PFD18B
64KX32
AS7C3364PFD32B
64KX36
AS7C3364PFD36B
128KX18
www.DataSheet4U.co6m4KX32
AS7C33128FT18B
AS7C3364FT32B
64KX36
AS7C3364FT36B
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
PL-SCD
PL-DCD
FT
: Pipelined Burst Synchronous SRAM - Single Cycle Deselect
: Pipelined Burst Synchronous SRAM - Double Cycle Deselect
: Flow-through Burst Synchronous SRAM
AS7C33128PFD18B
Speed
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
200/166/133 MHz
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
6.5/7.5/8.0/10 ns
1/31/05; v.1.2
Alliance Semiconductor
P. 2 of 19


Part Number AS7C33128PFD18B
Description 3.3V 128K x 18 pipeline burst synchronous SRAM
Maker Alliance Semiconductor Corporation
Total Page 19 Pages
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