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AS7C33128PFD18B - 3.3V 128K x 18 pipeline burst synchronous SRAM

Description

The AS7C33128PFD18B is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.

Features

  • Organization: 131,072 words × 18 bits.
  • Fast clock speeds to 200 MHz.
  • Fast clock to data access: 3.0/3.5/4.0 ns.
  • Fast OE access time: 3.0/3.5/4.0 ns.
  • Fully synchronous register-to-register operation.
  • Double-cycle deselect.
  • Asynchronous output enable control.
  • Available in 100-pin TQFP package www. DataSheet4U. com.
  • Individual byte write and global write.
  • Multip.

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Datasheet Details

Part number AS7C33128PFD18B
Manufacturer Alliance Semiconductor Corporation
File Size 583.99 KB
Description 3.3V 128K x 18 pipeline burst synchronous SRAM
Datasheet download datasheet AS7C33128PFD18B Datasheet

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  • AS7C33128PFD32B - (AS7C33128PFD32B / AS7C33128PFD36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
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  • AS7C33128PFD36B - (AS7C33128PFD32B / AS7C33128PFD36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
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  • AS7C33128PFS36A - (AS7C33128PFS32A / AS7C33128PFS36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM

Full PDF Text Transcription

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February 2005 ® AS7C33128PFD18B 3.3V 128K × 18 pipeline burst synchronous SRAM Features • Organization: 131,072 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Individual byte write and global write • • • • • • Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.
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