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AS7C33256PFS16A - (AS7C33256PFS16A / AS7C33256PFS18A) 3.3V 256K X 16/18 pipeline burst synchronous SRAM

Description

The AS7C33256PFS16A and AS7C33256PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 262,144 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.

Features

  • Organization: 262,144 words × 16 or 18 bits.
  • Fast clock speeds to 166 MHz in LVTTL/LVCMOS.
  • Fast clock to data access: 3.5/3.8/4.0/5.0 ns.
  • Fast OE access time: 3.5/3.8/4.0/5.0 ns.
  • Fully synchronous register-to-register operation.
  • “Flow-through” mode.
  • Single-cycle deselect - Dual-cycle deselect also available (AS7C33256PFD16A/ www. DataSheet4U. com AS7C33256PFD18A).
  • Pentium®.
  • compatible architecture and timing.
  • As.

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Datasheet Details

Part number AS7C33256PFS16A
Manufacturer Alliance Semiconductor Corporation
File Size 253.07 KB
Description (AS7C33256PFS16A / AS7C33256PFS18A) 3.3V 256K X 16/18 pipeline burst synchronous SRAM
Datasheet download datasheet AS7C33256PFS16A Datasheet

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  • AS7C33256PFS18A - (AS7C33256PFS16A / AS7C33256PFS18A) 3.3V 256K X 16/18 pipeline burst synchronous SRAM
  • AS7C33256PFS18B - 3.3V 256K X 18 pipeline burst synchronous SRAM
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  • AS7C33256PFS36A - (AS7C33256PFS32A / AS7C33256PFS36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM
  • AS7C33256PFD18B - 3.3V 256K x 18 pipeline burst synchronous SRAM
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  • AS7C33256FT18B - 3.3V 256K x 18 Flow Through Synchronous SRAM

Full PDF Text Transcription

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March 2001 ® AS7C33256PFS16A AS7C33256PFS18A 3.3V 256K × 16/18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 16 or 18 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns • Fast OE access time: 3.5/3.8/4.0/5.0 ns • Fully synchronous register-to-register operation • “Flow-through” mode • Single-cycle deselect - Dual-cycle deselect also available (AS7C33256PFD16A/ www.DataSheet4U.com AS7C33256PFD18A) • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package • Byte write enables • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.
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