Datasheet4U Logo Datasheet4U.com

AS7C332MNTF18A - 3.3V 2M x 18 Flowthrough SRAM

Description

The AS7C332MNTF18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 2,097,152 words × 18 bits and incorporates a LATE Write.

Features

  • Organization: 2,097,152 words × 18 bits NTD™architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package.
  • Byte write enables Clock enable for operation hold Multiple chip en.

📥 Download Datasheet

Datasheet Details

Part number AS7C332MNTF18A
Manufacturer Alliance Semiconductor Corporation
File Size 462.54 KB
Description 3.3V 2M x 18 Flowthrough SRAM
Datasheet download datasheet AS7C332MNTF18A Datasheet

📁 Similar Datasheet

  • AS7C33256NTD16A - 3.3V 256K X 16/18 SRAM (Alliance Semiconductor)
  • AS7C33256NTD18A - 3.3V 256K X 16/18 SRAM (Alliance Semiconductor)
  • AS7C33128NTD32A - 3.3V 128K X 32/36 SRAM (Alliance Semiconductor)
  • AS7C33128NTD36A - 3.3V 128K X 32/36 SRAM (Alliance Semiconductor)
  • AS7C31024 - 5V/3.3V 128K x 8 CMOS SRAM (Alliance Semiconductor)
  • AS7C31024A - 5V/3.3V 128K x 8 CMOS SRAM (Alliance Semiconductor)
  • AS7C31025 - 5V/3.3V 128K x 8 CMOS SRAM (Alliance Semiconductor)
  • AS7C31025C - 3.3V 128K x 8 CMOS SRAM (Alliance Semiconductor)
  • AS7C31026 - 5V/3.3V 64K x 16 CMOS SRAM (Alliance Semiconductor)
  • AS7C31026B - 3.3V 64K x 16 CMOS SRAM (Alliance Semiconductor)
Other Datasheets by Alliance Semiconductor Corporation

Full PDF Text Transcription

Click to expand full text
December 2004 ® AS7C332MNTF18A 3.3V 2M x 18 Flowthrough SRAM with NTDTM Features • • • • • • • • Organization: 2,097,152 words × 18 bits NTD™architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • • Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation www.DataSheet4U.
Published: |