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ADCMP604 Datasheet

Single-Supply LVDS Comparators

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Data Sheet
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply LVDS Comparators
ADCMP604/ADCMP605
FEATURES
Fully specified rail to rail at VCCI = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to VCCI + 0.2 V
Low glitch LVDS-compatible output stage
1.6 ns propagation delay
37 mW at 2.5 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAM
VCCI
VCCO
(ADCMP605 ONLY)
VP NONINVERTING
INPUT
VN INVERTING
INPUT
ADCMP604/
ADCMP605
LVDS
Q OUTPUT
Q OUTPUT
LE/HYS INPUT (ADCMP605
SDN INPUT
ONLY)
Figure 1.
GENERAL DESCRIPTION
The ADCMP604/ADCMP605 are very fast comparators fabricated
on the Analog Devices, Inc. proprietary XFCB2 process. These
comparators are exceptionally versatile and easy to use. Features
include an input range from VEE − 0.5 V to VCCI + 0.2 V, low noise,
LVDS-compatible output drivers, and TTL/CMOS latch inputs
with adjustable hysteresis and/or shut-down inputs.
The devices offer 1.5 ns propagation delays with 1 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single 2.5 V positive supply and a −0.5 V to +2.7 V input
signal range up to a 5.5 V positive supply with a −0.5 V to +5.7 V
input signal range. Split input/output supplies, with no sequencing
restrictions on the ADCMP605, support a wide input signal
range with greatly reduced power consumption.
The LVDS-compatible output stage is designed to drive any
standard LVDS input. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. High
speed latch and programmable hysteresis features are also provided
in a unique single-pin control option.
The ADCMP604 is available in a 6-lead SC70 package, and the
ADCMP605 is available in a 12-lead LFCSP.
Rev. C
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


Analog Devices Semiconductor Electronic Components Datasheet

ADCMP604 Datasheet

Single-Supply LVDS Comparators

No Preview Available !

ADCMP604/ADCMP605
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
1/15—Rev. B to Rev. C
Changes to Figure 4.......................................................................... 7
Change to Figure 16 Caption .......................................................... 9
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
11/14—Rev. A to Rev. B
Changes to Figure 4 and Table 6..................................................... 7
Changes to Figure 15 and Figure 16............................................... 9
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
Data Sheet
Applications Information .............................................................. 10
Power/Ground Layout and Bypassing..................................... 10
LVDS-Compatible Output Stage .............................................. 10
Using/Disabling the Latch Feature........................................... 10
Optimizing Performance........................................................... 10
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Points................................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
8/07—Rev. 0 to Rev. A
Changes to Features and General Description ..............................1
Changes to Electrical Characteristics Section ...............................3
Changes to Table 3.............................................................................6
Changes to Layout .............................................................................7
Changes to Figure 8...........................................................................8
Changes to Figure 14.........................................................................9
Changes to Power/Ground Layout and Bypassing Section, and
Using/Disabling the Latch Feature Section................................. 10
Changes to Comparator Hysteresis Section................................ 11
Changes to Crossover Bias Points Section .................................. 12
Changes to Ordering Guide .......................................................... 14
10/06—Revision 0: Initial Version
Rev. C | Page 2 of 14


Part Number ADCMP604
Description Single-Supply LVDS Comparators
Maker Analog Devices
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ADCMP604 Datasheet PDF






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