FEATURES
Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage Complementary outputs 3.5 ns propagation delay 12 mW at 3.3 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 50 dB −40°C to +125°C operation FUNCTIONAL BLOCK DIAGRAM VCCI VCCO VP NONINVERTING INPUT Q OUTPUT ADCMP603 VN INVERTING INPUT TTL Q OUTPUT LE/HYS INPUT SDN INPUT APPLICATIONS
High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) Figure 1. GENERAL DESCRIPTION
proprietary process. FEATURES
include an input range from VEE − 0.5 V to VCC + 0.2 V, low noise complementary TTL-/CMOS-compatible output drivers, latch inputs with adjustable hysteresis and a shutdown input.
Analog Devices
