FEATURES
Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCC + 0.2 V Low glitch LVDS-compatible output stage 1.6 ns propagation delay 37 mW at 2.5 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 60 dB −40°C to +125°C operation FUNCTIONAL BLOCK DIAGRAM VCCI VCCO (ADCMP605 ONLY) VP NONINVERTING INPUT Q OUTPUT ADCMP604/ ADCMP605 VN INVERTING INPUT LVDS Q OUTPUT APPLICATIONS
High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) LE/HYS INPUT SDN INPUT (ADCMP605 ONLY) Figure 1. GENERAL DESCRIPTION
FEATURES
include an input range from VEE − 0.5 V to VCC + 0.2 V, low noise, LVDS-compatible output drivers, and TTL/CMOS latch inputs with adjustable hysteresis and/or shutdown inputs.
Analog Devices
