Description
3 DSP Core Architecture 3 Memory Architecture 5 Bus Request and Bus Grant 6 DMA Controller 7 DSP Peripherals Architecture 7 Serial Peripheral Interface (SPI) Port 7 DSP Serial Port (SPORT) 8 Controller Area Network (CAN) Module 9 Analog-to-Digital Conversion System 9 Voltage Reference 9 P
Features
- ADSP-2199x, 16-bit, fixed-point DSP core with up to 160 MIPS sustained performance
48K words of on-chip RAM, as 32K words on-chip 24-bit program RAM, and 16K words on-chip, 16-bit data RAM
External memory interface Dedicated memory DMA controller for data/instruction
transfer between internal/external memory Programmable PLL and flexible clock generation circuitry
enables full-speed operation from low speed input clocks IEEE JTAG Standard 1149.1 test access port supports on-chip emulation and sy.
ADSP-21992 Datasheet
