CY14B104N Datasheet | Cypress

Features - - - - - - - - - - - - - Functional Description The Cypress CY14B104L/CY14B104N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K words of 8 bits each or 256K words of 16 bits each. The embedded nonvolatile elements incorporate Quantum Trap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable Quantum Trap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. 15 ns, 25 ns, and 45 ns access times Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) Hands off automatic STORE on power down with only a small capacitor STORE to Quantum Trap® nonvolatile elements initiated by software, device pin or Auto Store® on power down RECALL to SRAM initiated by software or power up Infinite read, write, and recall cycles 8 m A typical ICC at 200 ns cycle time 200,000 STORE cycles to Quantum Trap 20 year data retention Single 3V +20%, - 10% operation mercial and industrial temperatures FBGA and TSOP - II packages Ro HS pliance .. Logic Block Diagram VCAP Address A0 - A18 CE OE WE [1] [1] DQ0 - DQ7 CY14B104L CY14B104N HSB BHE BLE Note 1. Address A0 - A18 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A17 and Data DQ0 - DQ15 for x16 configuration. Cypress Semiconductor Corporation Document #: 001-07102 Rev. - F - 198 Champion Court - San Jose, CA 95134-1709 - 408-943-2600 Revised January 02, 2008 [+] Feedback PRELIMINARY CY14B104L, CY14B104N Pinouts Figure 1. Pin Diagram - 48...