Datasheet Summary
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256K x18 Pipelined SRAM with NoBL™ Architecture
Features
- Pin patible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P
- Supports 143-MHz bus operations with zero wait states
- Data is transferred on every clock
- Internally self-timed output buffer control to eliminate the need to use OE
- Fully registered (inputs and outputs) for pipelined operation
- Byte Write Capability
- 256K x 18 mon I/O architecture
- Single 3.3V power supply
- Fast clock-to-output times
- 4.0 ns (for 143-MHz device)
- 4.2 ns (for 133-MHz device)
- 5.0 ns (for 100-MHz device)
- 7.0 ns (for 80-MHz device)
- Clock Enable (CEN) pin to suspend operation
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