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CY7C1367C - 9-Mbit Pipelined DCD Sync SRAM

Download the CY7C1367C datasheet PDF (CY7C1366C included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 9-mbit pipelined dcd sync sram.

Description

The CY7C1366C/CY7C1367C SRAM i

Features

  • Supports bus operation up to 166 MHz.
  • Available speed grade is 166 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (double-cycle deselect).
  • Depth expansion without wait state.
  • 3.3 V.
  • 5% and + 10% core power supply (VDD).
  • 2.5 V/3.3 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 3.5 ns (for 166 MHz device).
  • Provide high performance 3-1-1-1 access rate.
  • User-selectable burst counter supp.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1366C-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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CY7C1366C CY7C1367C 9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM 9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 166 MHz ■ Available speed grade is 166 MHz ■ Registered inputs and outputs for pipelined operation ❐ Optimal for performance (double-cycle deselect) • Depth expansion without wait state ❐ 3.3 V – 5% and + 10% core power supply (VDD) ■ 2.5 V/3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.
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