CY7C1461AV25
Features
- No Bus Latency™ (No BL™) architecture eliminates dead cycles between write and read cycles
- Can support up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin-patible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow-through operation
- Byte Write capability
- 2.5V/1.8V I/O power supply
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
- Synchronous self-timed writes
- Asynchronous Output Enable
- CY7C1461AV25, CY7C1463AV25 available in JEDEC-standard lead-free 100-pin TQFP package, lead-free and non-lead-free 165-ball FBGA package. CY7C1465AV25 available in lead-free and non-lead-free 209-ball FBGA package.
- Three chip enables for simple depth expansion
- Automatic Power-down feature available using ZZ mode or CE deselect
- IEEE 1149.1 JTAG-patible Boundary Scan
-...
