* Pin compatible and functionally equivalent to ZBT
* Supports 250 MHz bus operations with zero wait states
* Available speed grades are 250, 200 and 167 MHz
* Internally self timed output buffer control to eliminate the need to use asynchronous OE
* Fully registered (inputs and
CY7C1460AV33 Datasheet (833.98 KB)
CY7C1460AV33
Cypress Semiconductor
833.98 KB
36-mbit pipelined sram.
CY7C1460AV33 CY7C1462AV33
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Archit.
📁 Related Datasheet
CY7C1460AV25 - 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM
(Cypress Semiconductor)
CY7C1460AV25 CY7C1462AV25 CY7C1464AV25
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture
Features
• Pin-patible and func.
CY7C1460BV25 - 36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM
(Cypress Semiconductor)
CY7C1460BV25 CY7C1462BV25
36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture
36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Ar.
CY7C1460KV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
(Cypress Semiconductor)
.
CY7C1460KV33 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
(Cypress Semiconductor)
CY7C1460KV33 CY7C1460KVE33 CY7C1462KVE33
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
36-Mbit (1M × 36/2M × 18) Pipeli.
CY7C1460KVE25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
(Cypress Semiconductor)
.
CY7C1460KVE33 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
(Cypress Semiconductor)
CY7C1460KV33 CY7C1460KVE33 CY7C1462KVE33
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
36-Mbit (1M × 36/2M × 18) Pipeli.
CY7C1460SV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
(Cypress)
CY7C1460SV25 CY7C1462SV25
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Archit.
CY7C146 - 2K x 8 Dual-Port Static RAM
(Cypress Semiconductor)
CY7C132, CY7C136 CY7C136A, CY7C142,
CY7C146
2K x 8 Dual-Port Static RAM
Features
■ True dual-ported memory cells that enable simultaneous reads of th.
