* Pin-compatible and functionally equivalent to ZBT™
* Supports 250-MHz bus operations with zero wait states
* Available speed grades is 250 MHz
* Internally self-timed output buffer control to eliminate the need to use asynchronous OE
* Fully registered (inputs and outputs) for
CY7C1462BV25 Datasheet (533.66 KB)
CY7C1462BV25
Cypress Semiconductor
533.66 KB
36-mbit (1 m x 36/2 m x 18) pipelined sram.
CY7C1460BV25 CY7C1462BV25 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Ar.
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