* Pin-compatible and functionally equivalent to Zero Bus Turnaround (ZBT™)
* Supports 250-MHz bus operations with zero wait states
* Available speed grades are 250, 200, and 167 MHz
* Internally self-timed output buffer control to eliminate the need to use asynchronous OE
* Fully
CY7C1462KVE33 Datasheet (1.32 MB)
CY7C1462KVE33
Cypress Semiconductor
1.32 MB
36-mbit (1m x 36/2m x 18) pipelined sram.
CY7C1460KV33 CY7C1460KVE33 CY7C1462KVE33 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC) 36-Mbit (1M × 36/2M × 18) Pipeli.
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