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Cypress Semiconductor Electronic Components Datasheet

CY7C2576KV18 Datasheet

72-Mbit QDR-II SRAM 4-Word Burst Architecture

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CY7C2561KV18, CY7C2576KV18
PRELIMINARY CY7C2563KV18, CY7C2565KV18
72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency) with ODT
Features
Configurations
Separate independent read and write data ports
Supports concurrent transactions
550 MHz clock for high bandwidth
With Read Cycle Latency of 2.5 cycles:
CY7C2561KV18 – 8M x 8
CY7C2576KV18 – 8M x 9
4-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both read and write
ports (data transferred at 1100 MHz) at 550 MHz
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Data valid pin (QVLD) to indicate valid data on the output
On-Die Termination (ODT) feature
Supported for D[x:0], BWS[x:0], and K/K inputs
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR™-II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR-I device with 1 cycle read latency
when DOFF is asserted LOW
Available in x8, x9, x18, and x36 configurations
Full data coherency, providing most current data
Core VDD = 1.8V± 0.1V; IO VDDQ = 1.4V to VDD [1]
Supports both 1.5V and 1.8V IO supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase Locked Loop (PLL) for accurate data placement
CY7C2563KV18 – 4M x 18
CY7C2565KV18 – 2M x 36
Functional Description
The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and
CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II+ architecture. Similar to QDR-II archi-
tecture, QDR-II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common IO devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR-II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C2561KV18), 9-bit words (CY7C2576KV18), 18-bit
words (CY7C2563KV18), or 36-bit words (CY7C2565KV18) that
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
These devices have an On-Die Termination feature supported
for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area,
and simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
550 MHz
550
x8 900
x9 900
x18 920
x36 1310
500 MHz
500
830
830
850
1210
450 MHz
450
760
760
780
1100
400 MHz
400
690
690
710
1000
Unit
MHz
mA
Note
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15887 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 24, 2009
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Cypress Semiconductor Electronic Components Datasheet

CY7C2576KV18 Datasheet

72-Mbit QDR-II SRAM 4-Word Burst Architecture

No Preview Available !

www.DataSheet.co.kr
PRELIMINARY
Logic Block Diagram (CY7C2561KV18)
CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
D[7:0]
8
A(20:0) 21
Address
Register
K
K
DOFF
VREF
WPS
NWS[1:0]
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
21 A(20:0)
Read Data Reg.
32
16
16
Control
Logic
RPS
Reg.
Reg.
Reg. 8
8
8
8
8
CQ
CQ
Q[7:0]
QVLD
Logic Block Diagram (CY7C2576KV18)
D[8:0]
9
A(20:0) 21
K
K
DOFF
VREF
WPS
BWS[0]
Address
Register
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
21 A(20:0)
Read Data Reg.
36
18
18
Control
Logic
RPS
Reg.
Reg.
Reg. 9
9
9
9
9
CQ
CQ
Q[8:0]
QVLD
Document Number: 001-15887 Rev. *E
Page 2 of 29
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Part Number CY7C2576KV18
Description 72-Mbit QDR-II SRAM 4-Word Burst Architecture
Maker Cypress Semiconductor
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