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CY7C4122KV13 - 144-Mbit QDR-IV XP SRAM

Description

The QDR™-IV XP (Xtreme Performance) SRAM is a high-performance memory device optimized to maximize the number of random transactions per second by the use of two independent bidirectional data ports.

These ports are equipped with DDR interfaces and designated as port A and port B respectively.

Features

  • e 144-Mbit QDR™-IV XP SRAM Configurations.
  • 144-Mbit density (8M × 18, 4M × 36).
  • Total Random Transaction Rate[1] of 2132 MT/s.
  • Maximum operating frequency of 1066 MHz.
  • Read latency of 8.0 clock cycles and write latency of 5.0 clock cycles.
  • Eight-bank architecture enables one access per bank per cycle.
  • Two-word burst on all accesses.
  • Dual independent bidirectional data ports.
  • Double data rate (DDR) data ports.
  • Supports concurrent read/write transacti.

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Datasheet Details

Part number CY7C4122KV13
Manufacturer Cypress Semiconductor
File Size 838.81 KB
Description 144-Mbit QDR-IV XP SRAM
Datasheet download datasheet CY7C4122KV13 Datasheet
Additional preview pages of the CY7C4122KV13 datasheet.

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Full PDF Text Transcription

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CY7C4122KV13/CY7C4142KV13 144-Mbit QDR™-IV XP SRAM Features e 144-Mbit QDR™-IV XP SRAM Configurations ■ 144-Mbit density (8M × 18, 4M × 36) ■ Total Random Transaction Rate[1] of 2132 MT/s ■ Maximum operating frequency of 1066 MHz ■ Read latency of 8.0 clock cycles and write latency of 5.0 clock cycles ■ Eight-bank architecture enables one access per bank per cycle ■ Two-word burst on all accesses ■ Dual independent bidirectional data ports ❐ Double data rate (DDR) data ports ❐ Supports concurrent read/write transactions on both ports ■ Single address port used to control both data ports ❐ DDR address signaling ■ Single data rate (SDR) control signaling ■ High-speed transceiver logic (HSTL) and stub series terminated logic (SSTL) compatible signaling (JESD8-16A compliant) ❐ I/O VDDQ = 1.
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