Description
The CY7C1355A/GVT71256ZB36 and CY7C1357A/ GVT71512ZB18 SRAMs are designed to eliminate dead cycles when transitions from READ to.
Features
- Zero Bus Latency, no dead cycles between write and read cycles.
- Fast clock speed: 133, 117, and 100 MHz.
- Fast access time: 6.5, 7.0, 7.5, and 8.0 ns.
- Internally synchronized registered outputs eliminate the need to control OE.
- Single 3.3V.
- 5% and +5% power supply VCC.
- Separate VCCQ for 3.3V or 2.5V I/O.
- Single R/W (READ/WRITE) control pin.
- Positive clock-edge triggered, address, data, and control signal registers fo.
