GVT71512D18 Datasheet | Cypress

( Data Sheet : .. ) 1CY7C1329 PRELIMINARY CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 256K x 36/512K x 18 Pipelined SRAM Features - - - - - - - - - - - - - - - - - - Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V - 5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs mon data inputs and data outputs Byte Write Enable and Global Write control Multiple chip enables for depth expansion: three chip enables for TA package version and two chip enables for B and T package versions Address pipeline capability Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications JTAG boundary scan for B and T package version Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), burst control inputs (ADSC, ADSP , and ADV), Write Enables (BWa, BWb, BWc, BWd, and BWE), and global write (GW). However, the CE2 chip enable input is only available for the TA package version. Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). Address, data inputs, and write...