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Data Delay Devices
Data Delay Devices

3D3428 Datasheet Preview

3D3428 Datasheet

MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE

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3D3428 pdf
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MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D3428 – LOW NOISE)
3D3428
ddaeltaay 3
devices, inc.
FEATURES
All-silicon, low-power CMOS technology
3.3V CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Leading- and trailing-edge accuracy
Programmable via serial or parallel interface
Increment range: 0.25 through 15.0ns
Delay tolerance: 0.5% (See Table 1)
Supply current: 2mA typical
Temperature stability: ±1.5% max (-40C to 85C)
Vdd stability: ±1.0% max (3.0V to 3.6V)
PACKAGES
IN 1 16 VDD
AE 2 15 OUT
SO/P0 3 14 MD
P1 4 13 P7
P2 5 12 P6
P3 6 11 SC
P4 7 10 P5
GND 8
9 SI
3D3428-xx DIP
IN
SO
AE
GND
1 8 VDD
2 7 OUT
3 6 SC
4 5 SI
3D3428Z-xx SOIC
IN
AE
SO/P0
P1
P2
P3
P4
GND
1
2
3
4
5
6
7
8
16 VDD
15 OUT
14 MD
13 P7
12 P6
11 SC
10 P5
9 SI
3D3428S-xx SOL
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3428 device is a versatile 8-bit programmable monolithic delay
line. The input (IN) is reproduced at the output (OUT) without inversion,
shifted in time as per the user selection. Delay values, programmed
either via the serial or parallel interface, can be varied over 255 equal
steps according to the formula:
Ti,nom = Tinh + i * Tinc
where i is the programmed address, Tinc is the delay increment (equal
to the device dash number), and Tinh is the inherent (address zero)
delay. The device features both rising- and falling-edge accuracy.
IN Signal Input
OUT Signal Output
MD Mode Select
AE Address Enable
P0-P7 Parallel Data Input
SC Serial Clock
SI Serial Data Input
SO Serial Data Output
VDD +3.3 Volts
GND Ground
The all-CMOS 3D3428 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a surface mount
16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D3428-0.25
3D3428-0.5
3D3428-1
3D3428-1.5
3D3428-2
3D3428-2.5
3D3428-4
3D3428-5
3D3428-7.5
3D3428-10
3D3428-15
DELAYS AND TOLERANCES
Inherent Delay
Delay
Delay (ns) Range (ns) Step (ns)
11.5 ± 2.0 63.75 ± 0.4 0.25 ± 0.15
11.5 ± 2.0 127.5 ± 0.8 0.50 ± 0.25
11.5 ± 2.0 255.0 ± 1.5 1.00 ± 0.50
11.5 ± 2.0 382.5 ± 2.3 1.50 ± 0.75
11.5 ± 2.0 510.0 ± 2.0 2.00 ± 1.00
13.0 ± 2.5 637.5 ± 2.5 2.50 ± 1.25
15.5 ± 4.0 1020 ± 4.0 4.00 ± 2.00
18.0 ± 5.0 1275 ± 4.0 5.00 ± 2.50
23.0 ± 7.5 1912.5 ± 6.0 7.50 ± 3.75
27.5 ± 10 2550 ± 8.0 10.0 ± 5.00
38.0 ± 15
3825 ± 12 15.0 ± 7.50
Rec’d Max
Frequency
6.25 MHz
3.12 MHz
1.56 MHz
1.04 MHz
781 KHz
625 KHz
390 KHz
312 KHz
208 KHz
156 KHz
104 KHz
INPUT RESTRICTIONS
Absolute Max Rec’d Min
Frequency
Pulse Width
77 MHz
80.0 ns
45 MHz
160.0 ns
22 MHz
320.0 ns
15 MHz
480.0 ns
11 MHz
640.0 ns
9.0 MHz
800.0 ns
5.6 MHz
1280.0 ns
4.5 MHz
1600.0 ns
3.0 MHz
2400.0 ns
2.2 MHz
3200.0 ns
1.5 MHz
4800.0 ns
Absolute Min
Pulse Width
6.5 ns
11.0 ns
22.0 ns
33.0 ns
44.0 ns
55.0 ns
88.0 ns
110.0 ns
165.0 ns
220.0 ns
330.0 ns
NOTES: Any delay increment between 0.25 and 15 ns not shown is also available as standard.
See application notes section for more details
2004 Data Delay Devices
Doc #04004
11/1/04
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1



Data Delay Devices
Data Delay Devices

3D3428 Datasheet Preview

3D3428 Datasheet

MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE

No Preview Available !

3D3428 pdf
3D3428
APPLICATION NOTES
GENERAL INFORMATION
The 8-bit programmable 3D3428 delay line
architecture is comprised of a number of delay
cells connected in series with their respective
outputs multiplexed onto the Delay Out pin (OUT)
by the user-selected programming data (the
address). Each delay cell produces at its output a
replica of the signal present at its input, shifted in
time. The change in delay from one address
setting to the next is called the increment, or
LSB. It is nominally equal to the device dash
number. The minimum delay, achieved by setting
the address to zero, is called the inherent delay.
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
DELAY ACCURACY
There are a number of ways of characterizing the
delay accuracy of a programmable line. The first
is the differential nonlinearity (DNL), also referred
to as the increment error. It is defined as the
deviation of the increment at a given address
from its nominal value. For most dash numbers,
the DNL is within 0.5 LSB at every address (see
Table 1: Delay Step).
The integrated nonlinearity (INL) is determined
by first constructing the least-squares best fit
straight line through the delay-versus-address
data. The INL is then the deviation of a given
delay from this line. For all dash numbers, the
INL is within 1.0 LSB at every address.
The relative error is defined as follows:
erel = (Ti – T0) – i * Tinc
where i is the address, Ti is the measured delay
at the i’th address, T0 is the measured inherent
delay, and Tinc is the nominal increment. It is very
similar to the INL, but simpler to calculate. For
most dash numbers, the relative error is less than
1.0 LSB at every address (see Table 1: Delay
Range).
The absolute error is defined as follows:
eabs = Ti – (Tinh + i * Tinc)
where Tinh is the nominal inherent delay. The
absolute error is limited to 1.5 LSB or 3.0 ns,
whichever is greater, at every address.
The inherent delay error is the deviation of the
inherent delay from its nominal value. It is limited
to 1.0 LSB or 2.0 ns, whichever is greater.
DELAY STABILITY
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The 3D3428 utilizes novel compensation circuitry
to minimize the delay variations induced by
fluctuations in power supply and/or temperature.
With regard to stability, the delay of the 3D3428
at a given address, i, can be split into two
components: the inherent delay (T0) and the
relative delay (Ti – T0). These components exhibit
very different stability coefficients, both of which
must be considered in very critical applications.
The thermal coefficient of the relative delay is
limited to ±250 PPM/C (except for the dash 0.25),
which is equivalent to a variation, over the -40C
to 85C operating range, of ±1.5% (±9% for the
dash 0.25) from the room-temperature delay
settings. The thermal coefficient of the inherent
delay is nominally +20ps/C for dash numbers 5
or less, and +30ps/C for all other dash numbers.
The power supply sensitivity of the relative delay
is ±1.0% (±3.0% for the dash 0.25) over the 3.0V
to 3.6V operating range, with respect to the delay
settings at the nominal 3.3V power supply. This
holds for all dash numbers. The sensitivity of the
inherent delay is nominally –5ps/mV for all dash
numbers.
INPUT SIGNAL CHARACTERISTICS
The frequency and/or pulse width (high or low) of
operation may adversely impact the specified
delay and increment accuracy of the particular
device. The reasons for the dependency of the
output delay accuracy on the input signal
characteristics are varied and complex.
Therefore a recommended maximum and an
absolute maximum operating input frequency and
a recommended minimum and an absolute
minimum operating pulse width have been
specified.
OPERATING FREQUENCY
The absolute maximum operating frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
Doc #04004
11/1/04
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2


Part Number 3D3428
Description MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE
Maker Data Delay Devices
Total Page 7 Pages
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