DFPAU-DP
Description
Global system clock Global system reset Chip select for read/write Data bus input Register address to read/write Data write enable datai[31:0]1 addr[4:2] we datao[31:0]1 irq Output Data bus output Output Interrupt request indicator 1 - data bus can be configured as 8-, 16- or 32- bit depends on processor’s bus size 2 - address bus is aligned to work with 8- (3:0), 16(3:1) or 32- (4:2) bit processors.
Key Features
- Direct replacement for C double, float software functions such as: +, -, *, /,==, !=,>=, <=, <, >
- Configurability of all available functions
- C interface supplied for all popular compilers: GNU C/C++, 8051 compilers
- No programming required
- IEEE-754 Double precision real format support - double type
- IEEE-754 www.DataSheet4U.com Single precision real format support - float type *
- DELIVERABLES
- Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted Netlist or/and plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet Synthesis scripts Example application Technical support ◊ IP Core implementation support ◊ 3 months maintenance ◊ ◊ ◊ ◊ * * *
- 8-bit, 16-bit 32-bit and 52-bit integers format supported - integer types
- Flexible arguments and result registers location
