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ESMT

M13L32321A Datasheet Preview

M13L32321A Datasheet

Double Data Rate SDRAM

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ESMT
DDR SDRAM
M13L32321A (2G)
512K x 32 Bit x 2 Banks
Double Data Rate SDRAM
Features
z Double-data-rate architecture, two data transfers per clock cycle
z Bi-directional data strobe (DQS)
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Two bank operation
z CAS Latency : 2, 2.5, 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
z Data mask (DM) for write masking only
z VDD = 3.3V ± 0.3V, VDDQ = 3.3V ± 0.3V
z Auto & Self refresh
z 15.6us refresh interval
Ordering Information
Product ID
M13L32321A -5BG2G
M13L32321A -6BG2G
M13L32321A -7.5BG2G
Max Freq.
200MHz (DDR400)
166MHz (DDR333)
133MHz (DDR266)
Package
Comments
144 ball FBGA
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
1/48




ESMT

M13L32321A Datasheet Preview

M13L32321A Datasheet

Double Data Rate SDRAM

No Preview Available !

ESMT
Functional Block Diagram
CLK
CLK
CKE
Clock
Generator
Address, BA
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
M13L32321A (2G)
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQS DM
DQ
CLK, CLK
DLL
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
2/48


Part Number M13L32321A
Description Double Data Rate SDRAM
Maker ESMT
Total Page 30 Pages
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