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M13D64322A-4.5BG2S - 512K x 32 Bit x 4 Banks LPDDR SDRAM

Download the M13D64322A-4.5BG2S datasheet PDF. This datasheet also covers the M13D64322A variant, as both devices belong to the same 512k x 32 bit x 4 banks lpddr sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

Ball Name Function A0~A10, BA0~BA1 Address inputs - Row address A0~A10 - Column address A0~ A7 A10/AP : AUTO Precharge BA0~BA1 : Bank selects (4 Banks) DQ0~DQ31 Data-in/Data-out RAS CAS WE VSS VDD DQS0~DQS3 Row address strobe Column address strobe Write enable Ground Power Bi-directional Data

Key Features

  • JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. Differential clock inputs (CLK and CLK ) Four bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, 16 & full page Special function support - DS (Drive Strength) - Deep Power Down Mode (DPD Mode) M13D64322A (2S) 512K x 32 Bit x 4 Banks Low Power DDR SDRAM All inputs except data & DM ar.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M13D64322A-ESMT.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by ESMT (Elite Semiconductor Microelectronics Technology)

Part Number Description
M13D64322A-4BG2S 512K x 32 Bit x 4 Banks LPDDR SDRAM
M13D64322A-5BG2S 512K x 32 Bit x 4 Banks LPDDR SDRAM
M13D64322A 512K x 32 Bit x 4 Banks LPDDR SDRAM
M13L32321A Double Data Rate SDRAM
M13S128168A-4.5BG2S 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ESMT LPDDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. Differential clock inputs (CLK and CLK ) Four bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, 16 & full page Special function support - DS (Drive Strength) - Deep Power Down Mode (DPD Mode) M13D64322A (2S) 512K x 32 Bit x 4 Banks Low Power DDR SDRAM All inputs except data & DM are sampled at the rising edge of the system clock(CLK) DQS is edge-aligned with data for READ; center-aligned with data for WRITE Data mask (DM) for write masking only VDD = 1.7V ~ 1.95V VDDQ = 1.7V ~ 1.95V Auto & Self refresh 15.