Description
The M52D256328A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits.
Features
- 1.8V power supply.
- LVCMOS compatible with multiplexed address.
- Four banks operation.
- MRS cycle with address key programs
- CAS Latency (3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave).
- EMRS cycle with address.
- All inputs are sampled at the positive going edge of the system clock.
- Special function support - PASR (Partial Array Self Refresh) - TCSR (Temperature Compensated Self Refresh) - DS (Driver Strength).
- DQM for maski.
M52D256328A-ESMT.pdf
