GS88018AT-150 srams equivalent, 512k x 18/ 256k x 32/ 256k x 36 9mb sync burst srams.
* FT pin for user-configurable flow through or pipeline operation
* Single Cycle Deselect (SCD) operation
* 2.5 V or 3.3 V +10%/
–10% core powe.
* JEDEC-standard 100-lead TQFP package Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tKQ tCycle Curr.
Applications
The GS88018/32/36AT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performan.
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