M24L816512SA
Features
‧Advanced low-power architecture
- High speed: 55 ns, 70 ns
- Wide voltage range: 2.7V to 3.6V
- Typical active current: 2 m A @ f = 1 MHz
- Typical active current: 11 m A @ f = f MAX
- Low standby power
- Automatic power-down when deselected
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M24L816512SA 8-Mbit (512K x 16) Pseudo Static RAM
Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). Writing to the device is acplished by taking Chip Enable( CE LOW) and Write Enable ( WE ) input LOW. If Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins(A0 through A18). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is acplished by taking Chip Enable ( CE LOW) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then...
