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EDS1216AATA - 128M bits SDRAM

Description

The EDS1216AATA is a 128M bits SDRAM organized as 2,097,152 words × 16 bits × 4 banks.

All inputs and outputs are synchronized with the positive edge of the clock.

It is packaged in 54-pin plastic TSOP (II).

Features

  • 3.3V power supply Clock frequency: 133MHz (max. ) Single pulsed /RAS ×16 organization 4 banks can operate simultaneously and independently.
  • Burst read/write operation and burst read/single write operation capability.
  • Programmable burst length (BL): 1, 2, 4, 8, full page.
  • 2 variations of burst sequence  Sequential (BL = 1, 2, 4, 8, full page)  Interleave (BL = 1, 2, 4, 8).
  • Programmable /CAS latency (CL): 2, 3.

📥 Download Datasheet

Datasheet Details

Part number EDS1216AATA
Manufacturer Elpida Memory
File Size 1.07 MB
Description 128M bits SDRAM
Datasheet download datasheet EDS1216AATA Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com DATA SHEET 128M bits SDRAM EDS1216AATA (8M words × 16 bits) Description The EDS1216AATA is a 128M bits SDRAM organized as 2,097,152 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 54-pin plastic TSOP (II). Pin Configurations /xxx indicate active low signal. 54-pin Plastic TSOP (II) VDD DQ0 VDDQ Features • • • • • 3.3V power supply Clock frequency: 133MHz (max.
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