Datasheet Summary
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DATA SHEET
128M bits SDRAM
EDS1216AABH, EDS1216CABH (8M words × 16 bits)
Description
The EDS1216AABH, EDS1216CABH are 128M bits SDRAM organized as 2,097,152 words × 16 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. Supply voltages are 3.3V (EDS1216AABH) and 2.5V (EDS1216CABH). They are packaged in 54-ball FBGA.
Pin Configurations
/xxx indicate active low signal.
54-ball FBGA
1 A
DQ15 VSSQ
VDDQ
DQ0
DQ14 DQ13 VDDQ
VSSQ
DQ2
DQ1
Features
- -
- -
- 3.3V and 2.5V power supply Clock frequency: 133MHz (max.) Single pulsed /RAS ×16 organization 4 banks can operate simultaneously and...