EM47EM1688MBB Key Features
- JEDEC Standard VDD/VDDQ = 1.35V-0.065/+0.1V
- Backward patible to VDD/ VDDQ = 1.5V ±0.075V
- All inputs and outputs are patible with SSTL_15
- Fully differential clock inputs (CK, /CK) operation
- Eight Banks
- Posted CAS by programmable additive latency
- Bust length: 4 with Burst Chop (BC) and 8
- CAS Write Latency (CWL): 5,6,7,8
- CAS Latency (CL): 6,7,8,9,10,11
- Write Latency (WL) =Read Latency (RL) -1