* Fast access time from clock: 4.5/5/5.4 ns
* Fast clock rate: 200/166/143MHz
* Fully synchronous operation
* Internal pipelined architecture
* 2M wor.

requiring high memory bandwidth and particularly well suited to high performance PC applications. Table 1. Key Specific.

Table 3. Pin Details Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. C.

EM63A165

EM63A165TS

EM6352

EM6353

EM6354

EM636165

EM636165-XXI

EM636327

EM637327

EM638165

EM638165TS

EM638325

EM639165