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XRK32308 - 3.3V ZERO DELAY BUFFER

General Description

FUNCTIONAL DESCRIPTION XRK32308 is a 3.3V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications.

The part has an on-chip PLL which locks to an input clock presented on the REF pin.

Key Features

  • Zero input-output propagation delay, adjustable by capacitive load on FB input.
  • Multiple configurations, see “Available XRK32308 Configurations” table.
  • Multiple low-skew outputs.
  • Two banks of four outputs, three-stateable by two select inputs.
  • 10-MHz to 120-MHz operating range.
  • 75ps typical cycle-to-cycle jitter (15pF, 66MHz).
  • Space-saving 16-pin 150-mil SOIC package or 16pin TSSOP.
  • 3.3V operation.
  • Industrial.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com MAY 2006 PRELIMINARY XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.2 GENERAL DESCRIPTION FUNCTIONAL DESCRIPTION XRK32308 is a 3.3V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FB pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 200 ps. XRK32308 has two banks of four outputs each. These can be controlled by the Select inputs as shown in Table 2, “Select Input Decoding,” on page 2.