XRK39910
Overview
- Eight zero delay outputs 12mA balanced drive outputs Output frequency: 15MHz to 85MHz <250ps of output to output skew Low Jitter: <200ps peak-to-peak 3 skew grades External feedback, internal loop filter Selectable positive synchronization or negative edge Synchronous output enable 3-level inputs for PLL range control PLL bypass for DC testing Available in SOIC package FIGURE
- PIN C ONFIGURATION
