Datasheet Details
| Part number | EMP19K03HPC |
|---|---|
| Manufacturer | Excelliance MOS |
| File Size | 423.10 KB |
| Description | Dual N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| Datasheet | EMP19K03HPC-ExcellianceMOS.pdf |
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Overview: EMP19K03HPC Dual N-Channel Logic Level Enhancement Mode Field Effect Transistor ▪Product Summary: ▪.
| Part number | EMP19K03HPC |
|---|---|
| Manufacturer | Excelliance MOS |
| File Size | 423.10 KB |
| Description | Dual N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| Datasheet | EMP19K03HPC-ExcellianceMOS.pdf |
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: Q1 Q2 BVDSS RDSON (MAX.)@VGS=10V RDSON (MAX.)@VGS=4.5V 30V 6.6mΩ 8.8mΩ 30V 2.4mΩ 3.4mΩ ID @TC=25℃ 62A 171A ID @TA=25℃ 20A 38A Dual N Channel MOSFET UIS, Rg 100% Tested RoHS & Halogen Free & TSCA Compliant ▪ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS Q1 Q2 Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current1 Avalanche Current Avalanche Energy Repetitive Avalanche Energy2 TC = 25 °C TC = 100 °C TA = 25 °C TA = 70 °C L = 0.1mH L = 0.05mH VGS ±20 ±20 ID 62 171 39 108 ID 20 38 16 30 IDM 114 294 IAS 34 65 EAS 57.8 211.3 EAR 28.9 105.6 Power Dissipation Power Dissipation TC = 25 °C TC = 100 °C TA = 25 °C TA = 70 °C PD 48 125 19 50 PD 5.2 6.3 3.3 4.0 Operating Junction & Storage Temperature Range Tj, Tstg -55 to 150 ▪100% UIS testing in condition of VD=25V, L=0.1mH, VG=10V, IL=21A,RG=25Ω,Rated VDS=30V N-CH_Q1 ▪100% UIS testing in condition of VD=25V, L=0.1mH, VG=10V, IL=39A,RG=25Ω,Rated VDS=30V N-CH_Q2 ▪THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Q1 Q2 Junction-to-Case RθJC 2.6 1.0 Junction-to-Ambient3 t≦10s RθJA Steady-State RθJA 24 20 58 52 1Pulse width limited by maximum junction temperature.
2Duty cycle < 1％ 3The value of RθJA is measured with the device mounted on 1in2 FR-4 board with 2oz.
Copper, in a still air environment with TA =25°C.
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