Datasheet Details
| Part number | DM7473 |
|---|---|
| Manufacturer | Fairchild (onsemi) |
| File Size | 39.48 KB |
| Description | Dual Master-Slave J-K Flip-Flop |
| Datasheet |
|
|
|
|
This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flops after a complete clock pulse.
While the clock is LOW the slave is isolated from the master.
| Part number | DM7473 |
|---|---|
| Manufacturer | Fairchild (onsemi) |
| File Size | 39.48 KB |
| Description | Dual Master-Slave J-K Flip-Flop |
| Datasheet |
|
|
|
|
| Part Number | Description | Manufacturer |
|---|---|---|
| DM7470 | AND Gated Positive Edge Triggered J-K Flip-Flop | National Semiconductor |
| DM7474 | Dual Positive-Edge-Triggered D Flip-Flops | National Semiconductor |
| DM7475 | Quad Latches | National Semiconductor |
| DM7476 | Dual Master-Slave J-K Flip-Flops | National Semiconductor |
| DM7400 | Quad 2-Input NAND Gates | National Semiconductor |
| Part Number | Description |
|---|---|
| DM7474 | Dual Positive-Edge-Triggered D-Type Flip-Flop |
| DM7474M | Dual Positive-Edge-Triggered D-Type Flip-Flop |
| DM7474N | Dual Positive-Edge-Triggered D-Type Flip-Flop |
| DM7476 | Dual Master-Slave J-K Flip-Flop |
| DM7400 | Quad 2-Input NAND Gates |
The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.