HDMP-0421 Datasheet PDF - Hewlett-Packard Port Bypass Circuits Specs

HDMP-0421 - Port Bypass Circuits

This page provides the datasheet information for the HDMP-0421, a member of the HDMP-0421_Hewlett Port Bypass Circuits family.

Datasheet Summary

Description

The HDMP-0421 is a Single Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR), and dual Signal Detect (SD) capability.

This configuration will control jitter accumulation while repeating incoming signals.

Features

Supports ANSI X3T11 1.0625 Gbps FC-AL Loop Configuration.
Supports 802.3z 1.25 Gbps Gigabit Ethernet (GE) Rates.
Single PBC, CDR, Dual Signal Detect (SD) in a Single Package.
Bidirectional, Symmetric Bypass Capability.
CDR in Bypass Path and Loop Path.
CDR Location Determined by Wiring Configuration of Pins on PCB (Patent Pending).
Envelope Detect on Cable Input (SD) for Both Directions.
Equalizers On All Inputs.
H.

Datasheet Details

Part number	HDMP-0421
Manufacturer	Hewlett-Packard
File Size	183.86 KB
Description	Port Bypass Circuits
Datasheet	HDMP-0421 Datasheet
Additional preview pages of the HDMP-0421 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions Technical Data Features • Supports ANSI X3T11 1.0625 Gbps FC-AL Loop Configuration • Supports 802.3z 1.25 Gbps Gigabit Ethernet (GE) Rates • Single PBC, CDR, Dual Signal Detect (SD) in a Single Package • Bidirectional, Symmetric Bypass Capability • CDR in Bypass Path and Loop Path • CDR Location Determined by Wiring Configuration of Pins on PCB (Patent Pending) • Envelope Detect on Cable Input (SD) for Both Directions • Equalizers On All Inputs • High Speed PECL I/Os Referenced to VCC • Buffered Line Logic (BLL) Outputs without External Bias Resistors • 0.4 W Typical Power at VCC = 3.

Published: Dec 28, 2006 |