HD74CDCF2509B driver equivalent, 140 mhz/ 0 to 85c operation 3.3-v phase-lock loop clock driver.
*
*
*
*
*
*
* Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1” Phase-lock loop clock distribution for synchronous D.
External feedback (FBIN) pin is used to synchronize the outputs to the clock input No external RC network required Suppo.
The HD74CDCF2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifica.
Image gallery
Download