HY57V64420HG 4 Banks x 4M x 4Bit Synchronous DRAM Datasheet

HY57V64420HG Key Features

Single 3.3±0.3V power supply All device pins are patible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0
Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type
1, 2, 4, 8 or Full page for Sequential Burst
1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks

Part Number	Description
HY57V641620ET	4-Bank x 1M x 16-Bits SDRAM
HY57V641620HG	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HG-I	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V643220C	4 Banks x 512K x 32Bit Synchronous DRAM
HY57V643220D	4 Bank x 512K x 32-Bit SDRAM