HY5V52F dram equivalent, 4banks x 2m x 32bits synchronous dram.
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* Voltage : VDD, VDDQ 3.3V All device pins are compatible with LVTTL interface 90Ball FBGA with 0.8mm of pin pitch All inputs and output.
which require wide data I/O and high bandwidth. HY5V52(L)F(P) is organized as 4banks of 2,097,152x32. HY5V52(L)F(P) is o.
and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / June. 2004 1
Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM
DESCRIPTI.
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