Datasheet Summary
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Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Document Title
4Bank x 2M x 32bits Synchronous DRAM
Revision History
Revision No. 0.1 History Initial Draft Draft Date Jun. 2004 Remark Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / June. 2004 1
Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM
DESCRIPTION
The Hynix HY5V52(L)F(P) series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high...